The present invention relates to a Content Addressable Memory (hereinafter referred to simply as "CAM") Device used in information processing devices and communications devices etc.
CAM compares an inputted data string and a stored data string and determines whether or not a coincident (HIT) or analogous data string exists within memory. An address of memory storing a coincident or analogous data string can then be outputted by this CAM.
In order to bring about these functions, individual CAM cells M used in CAM have the configuration of a usual SRAM cell with the addition of a comparing transistor, as in the example configuration shown in FIG. 2.
A CMOS type SRAM cell S is comprised of inverters X1 and X2 with inputs and outputs connected and NMOS transistors M1 and M2. Comparing of information stored within this SRAM and data inputted via a pair of bit lines BL and BL* (which is the signal for BL inverted) is carried out by NMOS transistors M3, M4 and M5.
In the following, a description is given of the basic operation of a CAM cell M using FIG. 2 (hereafter, the character "H" indicates a high level signal and the character "L" indicates a low level signal). The operation of writing data to a CAM cell M is basically the same as the operation for writing to a usual CMOS type SRAM comprising six transistors. When the NMOS transistors M1 and M2 are put on by the word line WL and BL="H" and BL*="L" are inputted to the bit line pair BL and BL*, the right side of the SRAM cell S is set to "H" and the right side is set to "L". These values are also held for the case when bit line pair BL and BL* are both set to "L" and the NMOS transistors M1 and M2 are both turned off. This state is defined as storage data "1". When BL="L" and BL*="H" are inputted, the inverse of this data is saved, with this inverse state being defined as storage data "0 ".
Next, a description is given of a search/compare operation. All of the word lines WL are set to an "L" level, the match lines ML are set to "H" and data is inputted to the search target bit line pair BL and BL*. The search target outer bit line pair BL and BL* are both held at "L" for masking purposes.
When storage data within the SRAM and data inputted at the bit line pair do not coincide using these searched bits, for example, when the storage data is "1", the right side of the SRAM cell S is "H". The gate of the NMOS transistor M4 therefore becomes "H" and the NMOS transistor M4 turns on.
At this time, as the data that does not coincide is "0", the data inputted to the bit line pair BL and BL* is BL="L" and BL*="H". The potential "H" of the bit line BL* is supplied to the gate of the NMOS transistor M5 via the NMOS transistor M4, the NMOS transistor M5 turns on and the potential of the match line ML is pulled down via the NMOS transistor M5.
On the other hand, if the storage data is "0", the non-coinciding data is "1". At this time, the data inputted to the bit line pair BL and BL* is BL="H" and BL*="L" so that the left side of SRAM cell S is "H". The gate of NMOS transistor M3 therefore becomes "H" and the NMOS transistor M3 is put on. The potential "H" of the bit line BL is then supplied to the gate of NMOS transistor M5 via NMOS transistor M3, NMOS transistor M5 goes on and the potential of the match line ML is pulled down via the NMOS transistor M5.
With respect to this, when the storage data within the SRAM cell S and the data inputted to the bit line pair coincide, at the NMOS transistors M3 and M4, the source potential of the NMOS transistor of the side to which "H" is supplied to the gate usually becomes "L" and this NMOS transistor cannot be put on. The NMOS transistor M5 therefore stays off and the potential of the match line ML is held at "H" without the potential of the match line ML being pulled down.
However, as the bit line pair BL and BL* are both "L" for non-search bits, the source side will always become "L" even when "H" is supplied to either of the gates of NMOS transistor M3 and NMOS transistor M4 and the NMOS transistor M5 therefore does not go on. This means that the potential of the match line ML is not pulled down.
As the match line ML is similarly connected to the CAM cells M of all of the bits for the same word, the match line is kept at "H" only when all of the bits not masked with respect to the storage data string and the inputted data string coincide.
Generally, CAM is equipped with a register for storing search result processing circuitry and select signals and a word select separation circuit etc. for selecting one from a plurality of selected words and is capable of outputting a plurality of words for which coincidence has been detected. When coincidence is detected for data within this plurality of words, there is an urgent need for a function for sequentially outputting this word information in the case where CAM is applied to the information processing field.
However, the plurality of select dividing circuits necessary to sequentially output a plurality of word information have to input match lines from all words and when these circuits are configured from basic logic circuitry, the logic depth increases dramatically when compared with the word lines. Operating speed therefore deteriorates and circuit surface area therefore increases.
A CAM is therefore desired where a plurality of word information can be sequentially outputted with circuitry that is small in scale.
Further, a CAM capable of high speed operations even for configurations where there are a large number of words is also desirable.